1. Field of the Invention
This invention relates to information stores and concerns a store for storing information in the form of a binary coded word.
2. Description of the Prior Art
A typical information store is arranged to store information in a binary code word, that is four binary digits or bits for each digit of a decimal number to be stored. It is important to ensure that the stored information remains correct and a simple step which may be taken to improve the reliability of a store is to add a parity bit, so that there are five bits per digit. Such a single parity bit can be used to detect whether there is an error but not what the error is. The next step is to use an error correcting code. This, for a four bit code, uses three extra bits which are generated in such a way that examination of the parity of three selected groups of four bits yields the address of the error. This may be visualized using an example:
______________________________________ Error Address 3 5 6 7 1 2 4 Bit Position 1 2 3 4 5 6 7 B.sub.1 B.sub.2 B.sub.4 B.sub.8 P.sub.1 P.sub.2 P.sub.4 Binary Code Parity Bit Code ______________________________________
Each parity bit has a "value" or weighting of 1, 2 or 4 such that an error in error address 3 will result in parity bits 1 and 2 being significant and 4 being non-significant on checking. P.sub.1 is the parity for bit positions 1, 2, 4, 5; P.sub.2 is the parity for positions 1, 3, 4, 6 and P.sub.4 is the parity for positions. 2, 3, 4, 7. The code may now be generated as follows:
______________________________________ Decimal B.sub.1 B.sub.2 B.sub.4 B.sub.8 P.sub.1 P.sub.2 P.sub.4 ______________________________________ 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 2 0 1 0 0 1 0 1 3 1 1 0 0 0 1 1 4 0 0 1 0 0 1 1 5 1 0 1 0 1 0 1 6 0 1 1 0 1 1 0 7 1 1 1 0 0 0 0 8 0 0 0 1 1 1 1 9 1 0 0 1 0 0 1 10 0 1 0 1 0 1 0 11 1 1 0 1 1 0 0 12 0 0 1 1 1 0 0 13 1 0 1 1 0 1 0 14 0 1 1 1 0 0 1 15 1 1 1 1 1 1 1 ______________________________________ EQU P.sub.1 = B.sub.1 + B.sub.2 + B.sub.8 . . . . (1) EQU p.sub.2 = b.sub.1 + b.sub.4 + b.sub.8 . . . . (2) EQU p.sub.4 = b.sub.2 + b.sub.4 + b.sub.8 . . . . (3)
and EQU 1 + 0 = 1 EQU 0 + 0 = 0 EQU 1 + 1 = 0
Suppose the number selected for the example is decimal 5. In binary form with the 3-bit parity code this is represented by 1 0 1 0 1 0 1.
Checking the parity: EQU B.sub.1 + B.sub.2 + B.sub.8 + P.sub.1 = 0 EQU b.sub.1 + b.sub.4 + b.sub.8 + p.sub.2 = 0 EQU b.sub.2 + b.sub.4 + b.sub.8 + p.sub.4 = 0
as in each case the sum is zero the coded information is correct.
Suppose, now that the bit B.sub.4, in bit position 3 is changed for example, the number becomes 1 0 0 0 1 0 1, and checking the parity: EQU B.sub.1 + B.sub.2 + B.sub.8 + P.sub.1 = 0 EQU b.sub.1 + b.sub.4 + b.sub.8 + p.sub.2 = 1 EQU b.sub.2 + b.sub.4 + b.sub.8 + p.sub.4 = 1
therefore, the error code address is P.sub.2 + P.sub.4 = 2 + 4 = Error address 6. Error address 6 is bit position 3 and the digit at this position must therefore be inverted to revert to the original correct information.
The major problem in using the above 3-bit parity code is that only a single error may be detected.